diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2020-03-16 22:46:57 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-03-26 02:06:45 +0000 |
| commit | 662da6cf7b181ea2787ba001d9cbb6d41916abec (patch) | |
| tree | 63a95b276913110c423c566db78b856650582ad3 /src/soc/intel/xeon_sp/acpi/iiostack.asl | |
| parent | a1b15172d7f0303e8a1fe147a778d73d4dc26b1a (diff) | |
soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.
This is a preparation for future work that will enable next
generation server CPU.
TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/acpi/iiostack.asl')
| -rw-r--r-- | src/soc/intel/xeon_sp/acpi/iiostack.asl | 90 |
1 files changed, 0 insertions, 90 deletions
diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl deleted file mode 100644 index 6750a4c56a..0000000000 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define MAKE_IIO_DEV(id,rt) \ - Device (PC##id) \ - { \ - Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) \ - Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) \ - Name (_UID, 0x##id) \ - Method (_PRT, 0, NotSerialized) \ - { \ - If (PICM) \ - { \ - Return (\_SB_.AR##rt) \ - } \ - Return (\_SB_.PR##rt) \ - } \ - External(\_SB.RT##id) \ - Method (_CRS, 0, NotSerialized) \ - { \ - Return (\_SB.RT##id) \ - } \ - Name (SUPP, 0x00) \ - Name (CTRL, 0x00) \ - Name (_PXM, 0x00) /* _PXM: Device Proximity */ \ - Method (_OSC, 4, NotSerialized) \ - { \ - CreateDWordField (Arg3, 0x00, CDW1) \ - If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) \ - { \ - CreateDWordField (Arg3, 0x04, CDW2) \ - If ((Arg2 > 0x02)) \ - { \ - CreateDWordField (Arg3, 0x08, CDW3) \ - } \ - SUPP = CDW2 \ - CTRL = CDW3 \ - If ((AHPE || ((SUPP & 0x16) != 0x16))) \ - { \ - CTRL &= 0x1E \ - Sleep (0x03E8) \ - } \ - /* Never allow SHPC (no SHPC controller in system) */ \ - CTRL &= 0x1D \ - /* Disable Native PCIe AER handling from OS */ \ - CTRL &= 0x17 \ - If ((Arg1 != One)) /* unknown revision */ \ - { \ - CDW1 |= 0x08 \ - } \ - If ((CDW3 != CTRL)) /* capabilities bits were masked */ \ - { \ - CDW1 |= 0x10 \ - } \ - CDW3 = CTRL \ - Return (Arg3) \ - } \ - Else \ - { \ - /* indicate unrecognized UUID */ \ - CDW1 |= 0x04 \ - IO80 = 0xEE \ - Return (Arg3) \ - } \ - } \ - } - -MAKE_IIO_DEV(00, 00) -MAKE_IIO_DEV(01, 10) -MAKE_IIO_DEV(02, 20) -MAKE_IIO_DEV(03, 28) - -#if MAX_SOCKET > 1 -MAKE_IIO_DEV(06, 40) -MAKE_IIO_DEV(07, 50) -MAKE_IIO_DEV(08, 60) -MAKE_IIO_DEV(09, 68) -#endif |