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authorAndrey Petrov <anpetrov@fb.com>2020-03-22 22:16:03 -0700
committerAndrey Petrov <anpetrov@fb.com>2020-03-26 18:13:35 +0000
commitb75bcc978af50dc409b5356abd33b064029480bb (patch)
treee10fb054547ee8375410cccd005b344495ccc54c /src/soc/intel/xeon_sp/Makefile.inc
parent5e5d9c2d1be190b00fec9e981cbe8bd89a62bb50 (diff)
mb/ocp/tiogapass: Properly configure early serial output
Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible. This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible. TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock. Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/Makefile.inc')
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