diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2020-03-20 12:08:32 -0700 |
|---|---|---|
| committer | Andrey Petrov <anpetrov@fb.com> | 2020-03-26 18:13:51 +0000 |
| commit | 2e410757efb824555191d8afd78cf79ab5ba6049 (patch) | |
| tree | bfd92989b163c3166c7e0911f2cbf37bf2e2b1b1 /src/soc/intel/xeon_sp/Makefile.inc | |
| parent | b75bcc978af50dc409b5356abd33b064029480bb (diff) | |
soc/intel/xeon_sp: Add basic Cooperlake-SP support
This adds barebones support.
What works:
* Linux kernel boots fine
* SIRQ and PCH interupts work fine (only in IOAPIC mode)
* PCH devices are usable
What doesn't:
* MP init is not there yet, only 1 CPU is up
* SMM is not supported
* GPIO is not available
* All IIO and extended bus numbers enumeration is not yet available
* Warm reset flow is untested
* MRC cache save/load
TEST=boots into Linux
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I7c987badc3c53f16ad178369c7e0906d6596e465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39713
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/Makefile.inc')
| -rw-r--r-- | src/soc/intel/xeon_sp/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index e05fea2448..1459ee932a 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -16,6 +16,7 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx +subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c romstage-y += romstage.c reset.c util.c spi.c |