diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-10-22 14:13:14 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-05 00:02:07 +0000 |
| commit | 1410224cf476ed5e666deffcbbc455055632add1 (patch) | |
| tree | 23f3df4f4588eb9de5efd8fb74289e1e62667724 /src/soc/intel/xeon_sp/Makefile.inc | |
| parent | 6c49f40b6e6342b7acb47cb0a57fa10269e3d4c9 (diff) | |
soc/intel/xeon_sp: Use common cpu/intel romstage entry
This removes some boilerplate like starting the console and also adds
a "start of romstage" timestamp.
Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/Makefile.inc')
| -rw-r--r-- | src/soc/intel/xeon_sp/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 07fe3debb4..a10075ab04 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,6 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c +romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c ramstage-y += memmap.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c |