soc/intel/xeon_sp: Enable PMC support

PMC support was not enabled on Xeon_sp platforms. This involves turning
on SOC_INTEL_COMMON_BLOCK_PMC and then adding the proper hooks in SOC
specific code.  This patch leverages code from the Skylake project and
adds the bare minimum hooks to leverage PMC common code. Most
importantly this enables power management registers located in the PMC
device (under ACPI_BASE_ADDRESS). Access to this device is also needed
for SMM setup and handling.

TEST=build for Tiogapass and enable the following Kconfig options:
	select SOC_INTEL_COMMON_BLOCK_PMC
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
        select CPU_INTEL_COMMON_SMM

Boot the system and ensure pmbase is programmed. (Look for pmbase in
debug messages). Secondly check that SMIs are enabled by looking at the
debug messages (search for "Enabling SMIs") and verifying in HW by
reading IO port 0x530.

Change-Id: I6d57a8282a8b6dc4314f156c39deb09535575cbd
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 94c1764659..3bbf6b725e 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -8,6 +8,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
 bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
 romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
 postcar-y += spi.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include