diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-12 21:17:56 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-20 10:18:46 +0000 |
| commit | 3d802535cbf222d403e0d7d5cc6632546333a4c4 (patch) | |
| tree | d81070cb4e983a44e790481e22d1746b699d0a22 /src/soc/intel/xeon_sp/Makefile.inc | |
| parent | 6e425e1275a7638eb4b42b4fdec23f5674d086f5 (diff) | |
soc/intel/xeon_sp: Set coreboot defined IOAPIC and HPET BDF
Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes
coreboot in control of these settings.
Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/Makefile.inc')
| -rw-r--r-- | src/soc/intel/xeon_sp/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index a10075ab04..2e50e64c25 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c -ramstage-y += memmap.c +ramstage-y += memmap.c pch.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c postcar-y += spi.c |