soc/intel: Add Intel Xeon Scalable Processor support

This patch adds support for Intel Xeon-SP.

This patch is developed and verified with Skylake Scalable
Processor, which is a processor in Xeon-SP family. The code
is expected to be reusable for future geneations of Xeon-SP
processors, and will be updated with smaller targeted
patches accordingly, to add support for additional Xeon-SP
processors, to add features, and to improve the code base.

The Skylake-SP FSP is based on FSP 2.0. The FSP is a
proof-of-concept build. The binary is not shared in public,
when this patch is upstreamed.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 59 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
new file mode 100644
index 0000000000..9ad3e77b35
--- /dev/null
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -0,0 +1,59 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 - 2020 Intel Corporation
+## Copyright (C) 2019 - 2020 Facebook Inc
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+ifeq ($(CONFIG_SOC_INTEL_XEON_SP),y)
+
+subdirs-y += ../../../cpu/intel/microcode
+subdirs-y += ../../../cpu/intel/turbo
+subdirs-y += ../../../cpu/x86/lapic
+subdirs-y += ../../../cpu/x86/mtrr
+subdirs-y += ../../../cpu/x86/tsc
+subdirs-y += ../../../cpu/x86/cache
+subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm
+
+bootblock-y += bootblock/bootblock.c
+bootblock-y += spi.c
+
+postcar-y += soc_util.c
+postcar-y += spi.c
+
+romstage-y += soc_util.c
+romstage-y += reset.c
+romstage-y += romstage.c
+romstage-y += soc_util.c
+romstage-y += spi.c
+romstage-y += hob_display.c
+romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
+romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
+
+ramstage-y += soc_util.c
+ramstage-y += uncore.c
+ramstage-y += reset.c
+ramstage-y += chip.c
+ramstage-y += soc_util.c
+ramstage-y += lpc.c
+ramstage-y += cpu.c
+ramstage-y += spi.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
+ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
+ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
+ramstage-y += hob_display.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/include
+CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)
+
+endif ## CONFIG_SOC_INTEL_XEON_SP