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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2023-06-30 14:13:58 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-12 13:56:32 +0000 |
| commit | 8dc16a9ce2ad7ca55cde4ecc6fdacded471d5e8f (patch) | |
| tree | 45a9dc76dbd933d0d02ec07177355977f9a0dd2d /src/soc/intel/tigerlake | |
| parent | 1aa5caf2acc1821f109101308042969a763d4c20 (diff) | |
soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset name
Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions