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authorDuncan Laurie <dlaurie@google.com>2020-10-10 00:18:08 +0000
committerDuncan Laurie <dlaurie@chromium.org>2020-11-20 00:24:53 +0000
commite997d85e3be50cda1ffdcf4d76014b713fe4951b (patch)
tree43fc12b32f3a151c8e58f82b29c6928fb7adda2f /src/soc/intel/tigerlake
parent64bc26ad1553eec6bbbd6deac21a3e79ca7ce455 (diff)
soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
This SOC overrides the common PMC device and instantiates the PMC device in the SSDT. It needs to call the common PMC function to provide the IPC mailbox method. The common PCIe RTD3 driver can also be enabled which will allow mainboards to enable Runtime D3 power control for PCIe devices. BUG=b:160996445 TEST=boot on volteer with this driver enabled for the NVMe device in the devicetree and disassemble the SSDT to ensure the RTD3 code is present. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/46261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/Kconfig1
-rw-r--r--src/soc/intel/tigerlake/pmc.c5
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 507f87100d..e117842e7f 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
+ select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c
index dbf3671af7..c5a4ae526a 100644
--- a/src/soc/intel/tigerlake/pmc.c
+++ b/src/soc/intel/tigerlake/pmc.c
@@ -13,6 +13,7 @@
#include <drivers/intel/pmc_mux/chip.h>
#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/pmc_ipc.h>
#include <intelblocks/rtc.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -119,6 +120,10 @@ static void soc_pmc_fill_ssdt(const struct device *dev)
acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE);
acpigen_write_resourcetemplate_footer();
+ /* Define IPC Write Method */
+ if (CONFIG(PMC_IPC_ACPI_INTERFACE))
+ pmc_ipc_acpi_fill_ssdt();
+
acpigen_pop_len(); /* PMC Device */
acpigen_pop_len(); /* Scope */