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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2020-11-19 14:09:47 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-11-23 16:44:59 +0000 |
| commit | de20b28fe48be9f279f34469f585f9b3aa6db818 (patch) | |
| tree | c0abe0e1da68d7b2860ce0f8e0dd0dc7561442b2 /src/soc/intel/tigerlake | |
| parent | 93859e319e81f975db135c78d4c1494357b0aee8 (diff) | |
mb/google/zork: correct USB2 phy TXVREFTUNE0 parameter name
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune
BUG=None
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions