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authorArthur Heymans <arthur@aheymans.xyz>2019-11-11 12:29:56 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-12 18:28:52 +0000
commitc6872f5524c70087d83d97f45bfbe55f1989f2d6 (patch)
tree0ebe95b7c943689a04a6e48632156a7a75006dab /src/soc/intel/tigerlake
parentb6768370d1e15c6516faee6aad8371747458d3b7 (diff)
soc/intel/tigerlake: Remove FSP-T option in Kconfig
This code lacks the temp_ram_init_params sybols so the FSP-T option so it would fail to build. Change-Id: Ie7d75943d89a964d0189f921fc433e4b9adfb0c5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/Kconfig28
1 files changed, 2 insertions, 26 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c0fb7080e8..2824e52558 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -50,6 +50,8 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select INTEL_CAR_NEM_ENHANCED
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER
@@ -174,32 +176,6 @@ config CBFS_SIZE
hex
default 0x200000
-choice
- prompt "Cache-as-ram implementation"
- default USE_TIGERLAKE_CAR_NEM_ENHANCED
- help
- This option allows you to select how cache-as-ram (CAR) is set up.
-
-config USE_TIGERLAKE_CAR_NEM_ENHANCED
- bool "Enhanced Non-evict mode"
- select SOC_INTEL_COMMON_BLOCK_CAR
- select INTEL_CAR_NEM_ENHANCED
- help
- A current limitation of NEM (Non-Evict mode) is that code and data
- sizes are derived from the requirement to not write out any modified
- cache line. With NEM, if there is no physical memory behind the
- cached area, the modified data will be lost and NEM results will be
- inconsistent. ENHANCED NEM guarantees that modified data is always
- kept in cache while clean data is replaced.
-
-config USE_TIGERLAKE_FSP_CAR
- bool "Use FSP CAR"
- select FSP_CAR
- help
- Use FSP APIs to initialize and tear down the Cache-As-Ram.
-
-endchoice
-
config FSP_HEADER_PATH
string "Location of FSP headers"
default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/"