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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-21 19:31:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:24:41 +0000 |
| commit | 825332d3c9eb4c32b9e2f8eb54bcc838b1c00bb3 (patch) | |
| tree | 85c887f6a2fdcad5b1cab1f6ba0ed8310a009c8e /src/soc/intel/tigerlake | |
| parent | 6e5aabd58aa3d87d81ed39ef7f5219c7bef82e84 (diff) | |
nb/intel/sandybridge: Factor out timing tables
The timing tables for Sandy Bridge are a subset of Ivy Bridge's tables.
Move the latter to a common place, and use it for both generations.
Tested on Asus P8Z77-V LX2 with an i7-2600 and an i5-3330, both work.
Change-Id: Id14227febf4eebb8a2b4d2d4f37759d0f42648c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39735
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions