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| author | Furquan Shaikh <furquan@google.com> | 2020-03-26 15:45:58 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-02 16:54:19 +0000 |
| commit | 35bff432e5456acec8e68adca6b496fda53c6c57 (patch) | |
| tree | 06bace7021fc980ba381805da7a049f857e7207d /src/soc/intel/tigerlake | |
| parent | 5b1f335ef8aed95e01f040bc7074fb00acc8ab7e (diff) | |
soc/intel/tigerlake: Add macros and SPD information for DDR4
This change adds new memory topologies (SODIMM, MIXED) that are
supported by DDR4 and macros required for DDR4 support.
Memory initialization support for DDR4 will be added in a follow-up
change.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/meminit.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index aab155e43c..a2fb3f4334 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -17,8 +17,13 @@ #define LPDDR4X_CHANNELS 8 #define LPDDR4X_BYTES_PER_CHANNEL 2 +#define DDR4_CHANNELS 2 +#define DDR4_BYTES_PER_CHANNEL 8 + enum mem_topology { MEMORY_DOWN, /* Supports reading SPD from CBFS or in-memory pointer. */ + SODIMM, /* Supports reading SPD using SMBus (only for DDR4). */ + MIXED, /* CH0 = MD, CH1 = SODIMM (only for DDR4). */ }; enum md_spd_loc { @@ -43,6 +48,17 @@ struct spd_info { size_t data_len; }; }; + + /* + * SPD info for SODIMM topology. + * Leave addr_dimmN as 0 for any DIMMs that are not populated. + */ + struct { + /* SMBus address for DIMM0 within the channel. */ + uint8_t addr_dimm0; + /* SMBus address for DIMM1 within the channel. */ + uint8_t addr_dimm1; + } smbus_info[DDR4_CHANNELS]; }; /* Board-specific memory configuration information */ |