diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-01 22:28:03 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-28 21:28:19 +0000 |
| commit | 310c7637daba6ba4e9249928e5cd0e45ef4661e1 (patch) | |
| tree | 43416b3a09fd9130976254cb1317c47c80c08516 /src/soc/intel/tigerlake | |
| parent | 72e49cef806467a16d4d57858ad38b092c0a61ad (diff) | |
soc/intel: deduplicate ACPI timer emulation
The code for enabling ACPI timer emulation is the same for the SoCs
SKL, CNL, ICL, TGL, JSL and EHL. Deduplicate it by moving it to
common code.
APL differs in not having the delay settings. However, the bits are
marked as "spare" and BWG mentions there are no "reserved bit checks
done". Thus, we can write them unconditionally without any effect.
Note: The ACPI timer emulation can only be used by SoCs with microcode
supporting CTC (Common Timer Copy) / ACPI timer emulation.
Change-Id: Ied4b312b6d53e80e71c55f4d1ca78a8cb2799793
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/cpu.c | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d7234e7191..36dfa1b738 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -23,7 +23,6 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/pm.h> #include <soc/soc_chip.h> static void soc_fsp_load(void) @@ -62,25 +61,6 @@ static void configure_misc(void) wrmsr(MSR_POWER_CTL, msr); } -static void enable_pm_timer_emulation(void) -{ - msr_t msr; - - if (!CONFIG_CPU_XTAL_HZ) - return; - - /* - * The derived frequency is calculated as follows: - * (clock * msr[63:32]) >> 32 = target frequency. - * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. - */ - msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; - /* Set PM1 timer IO port and enable */ - msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | - EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); - wrmsr(MSR_EMULATE_PM_TIMER, msr); -} - /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -97,7 +77,6 @@ void soc_core_init(struct device *cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); - /* Enable PM timer emulation */ enable_pm_timer_emulation(); /* Enable Direct Cache Access */ |