diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-05-05 09:10:13 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:09:50 +0000 |
| commit | 165efa1b863ad8c35646beda6ddd76075c5674a2 (patch) | |
| tree | 66b940b7aebb07ba462d60ae822a938bc2d70f4a /src/soc/intel/tigerlake | |
| parent | f381d97856854a4b43c0acdae9aaff991837ce64 (diff) | |
soc/intel/tigerlake: Disable VMD
It's already disabled by FSP default but disable VMD by devicetree
to remove dependency with FSP default setting.
BUG=None
Branch=None
Test=Build TGLRVP and boot up and check FSP log for checking VMD is
disabled.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ief81fe481b94abed9754881cf1f454999fafa52e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41061
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 7 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pci_devs.h | 4 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 850cdbd169..611a61035d 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -214,6 +214,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->CnviMode = 0; + /* VMD */ + dev = pcidev_path_on_root(SA_DEVFN_VMD); + if (dev) + params->VmdEnable = dev->enabled; + else + params->VmdEnable = 0; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index d76c4a105b..ee3e894a92 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -54,6 +54,10 @@ #define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) #define SA_DEV_TCSS_DMA1 PCI_DEV(0, SA_DEV_SLOT_TCSS, 3) +#define SA_DEV_SLOT_VMD 0x0e +#define SA_DEVFN_VMD PCI_DEVFN(SA_DEV_SLOT_VMD, 0) +#define SA_DEV_VMD PCI_DEV(0, SA_DEV_SLOT_VMD, 0) + /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) |