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authorAngel Pons <th3fanbus@gmail.com>2020-09-25 10:20:11 +0200
committerNico Huber <nico.h@gmx.de>2020-09-26 11:42:28 +0000
commita32df26ec0759bbac2080f6d9a437320f5d61157 (patch)
tree8ed78db76ec9fb4236689db86f1884c4c7aacc47 /src/soc/intel/tigerlake
parent2db779079585ed894189fad98a1a57b365e78d98 (diff)
arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/Kconfig5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index a722144fdd..7e143c10d7 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -8,10 +8,7 @@ if SOC_INTEL_TIGERLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_RAMSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_VERSTAGE_X86_32
+ select ARCH_ALL_STAGES_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS