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| author | Shuo Liu <shuo.liu@intel.com> | 2024-03-06 00:24:02 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-03-12 11:32:42 +0000 |
| commit | a0b7c06d07813af1484f3a90e9dc37cc4d041fa4 (patch) | |
| tree | 7f562b3a3468d194cfb6e4a0d04e2f1b6422782a /src/soc/intel/tigerlake | |
| parent | a454b6293743f12c8387a7b6a15f0b29715e39d6 (diff) | |
soc/intel/xeon_sp: Rewrite acpi_create_satc
SATC is for RCiEPs (Root Complex Integrated EndPoints) but not
limited to IOAT domains. Rewrite the func by iterating all domains
and its RCiEPs. Currently the codes only support 1 PCIe segment.
TEST=intel/archercity CRB
coreboot SATC generation logs are unchanged before and after.
Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81049
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions