diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-03-29 11:26:11 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-04-11 06:16:59 +0000 |
| commit | 88381c94801ed5326cc1c840968b359b57ff2ef2 (patch) | |
| tree | de0f9258a216f60517a73ffa22d610f817a59a50 /src/soc/intel/tigerlake | |
| parent | 9bc5b0097bacf456306e05a95a8b86440d405a17 (diff) | |
soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
This patch binds all FSP-M and FSP-S UPDs required for serial
redirection with `FSP_ENABLE_SERIAL_DEBUG` config to allow coreboot to
choose when to enable FSP debug output redirection to serial port.
For example:
PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S
SerialDebugMrcLevel => For controllig MRC debug level.
With this change FSP debug output will only be enabled when the user
enables `FSP_ENABLE_SERIAL_DEBUG` from site-local config with coreboot
serial image.
BUG=b:225544587
TEST=Able to build and boot brya. Also, the FSP debug log is exactly
the same before and with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63167
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
0 files changed, 0 insertions, 0 deletions