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authorSubrata Banik <subratabanik@google.com>2022-01-07 13:40:19 +0000
committerSubrata Banik <subratabanik@google.com>2022-01-19 09:57:47 +0000
commit56ab8e2aae25efc839daeb56d5922e66d2680aec (patch)
tree2790032028d9ddba711fe08a3eaab3105d571acd /src/soc/intel/tigerlake
parent6ac5dc2ca6a6b09d1b0156c2db6aa1385ccaf13e (diff)
soc/intel/common/cpu: Use SoC overrides to get CPU privilegeĀ level
This patch implements a SoC overridesĀ to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/tigerlake')
-rw-r--r--src/soc/intel/tigerlake/cpu.c8
-rw-r--r--src/soc/intel/tigerlake/include/soc/msr.h4
2 files changed, 11 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index a9aa8ffc53..d225c504c8 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -23,6 +23,14 @@
#include <soc/soc_chip.h>
#include <types.h>
+bool cpu_soc_is_in_untrusted_mode(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(MSR_BIOS_DONE);
+ return !!(msr.lo & ENABLE_IA_UNTRUSTED);
+}
+
static void soc_fsp_load(void)
{
fsps_load();
diff --git a/src/soc/intel/tigerlake/include/soc/msr.h b/src/soc/intel/tigerlake/include/soc/msr.h
index 954fce0a82..5bdbf92e8b 100644
--- a/src/soc/intel/tigerlake/include/soc/msr.h
+++ b/src/soc/intel/tigerlake/include/soc/msr.h
@@ -5,6 +5,8 @@
#include <intelblocks/msr.h>
-#define MSR_VR_MISC_CONFIG2 0x636
+#define MSR_BIOS_DONE 0x151
+#define ENABLE_IA_UNTRUSTED (1 << 0)
+#define MSR_VR_MISC_CONFIG2 0x636
#endif