diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-10 18:17:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-11 03:14:05 +0000 |
| commit | 3999aa6cdb1e1ed1a415aa79903e21193079eca6 (patch) | |
| tree | 782ba019df102e7794652ca48c7f77c0eff1bd5f /src/soc/intel/tigerlake | |
| parent | 86e53267c405e817bbda7d8c8f55c2a52fac6953 (diff) | |
soc/intel/tigerlake: Clean up systemagent.h
List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I82fc362589389081b1b1856524a972b780af9a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45256
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/systemagent.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index fca9b2b05a..437356d5e0 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,40 +15,40 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define CAPID0_A 0xe4 -#define VTD_DISABLE (1 << 23) +#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) -#define BIOS_RESET_CPL 0x5da8 +/* MCHBAR offsets */ #define GFXVTBAR 0x5400 #define EDRAMBAR 0x5408 #define VTVC0BAR 0x5410 #define REGBAR 0x5420 +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define BIOS_RESET_CPL 0x5da8 +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 #define IPUVTBAR 0x7880 #define TBT0BAR 0x7888 #define TBT1BAR 0x7890 #define TBT2BAR 0x7898 #define TBT3BAR 0x78A0 + #define MAX_TBT_PCIE_PORT 4 -#define VTBAR_ENABLED 0x01 +#define VTBAR_ENABLED 0x01 #define VTBAR_MASK 0x7ffffff000ull -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 - -#define IMRBASE 0x6A40 -#define IMRLIMIT 0x6A48 - static const struct sa_mmio_descriptor soc_vtd_resources[] = { - { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, - { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, - { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, - { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, - { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, - { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, - { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, + { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, + { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, + { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, + { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, + { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, + { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, + { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, }; #define V_P2SB_CFG_IBDF_BUS 0 |