diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-06-01 06:54:44 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-06-04 14:44:04 +0000 |
| commit | 0b92aa618fbb73363501b8bfb8e9f51bdd9e3b3e (patch) | |
| tree | f73dce20d1a01981d62969afc3b043ca9329d74c /src/soc/intel/tigerlake | |
| parent | de91780c3089e8a46be8ee7a196acaefa6bcf115 (diff) | |
soc/intel: Rename heci_init to cse_init
This patch renames heci_init() to cse_init() as HECI initialization
should have a bigger scope than just initializing the CSE
(a.k.a HECI1 alone).
BUG=none
TEST=Able to build and boot google/taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 872cca5c52..3c6e634f38 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -131,7 +131,7 @@ void mainboard_romstage_entry(void) /* Program SMBus base address and enable it */ smbus_common_init(); /* initialize Heci interface */ - heci_init(HECI1_BASE_ADDRESS); + cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); |