diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-01 21:26:42 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-11 20:49:53 +0000 |
| commit | 8a6c34e8ba9862814e53ad4f9b04ae1f2b9d4b49 (patch) | |
| tree | b4edf89d40b02f27ba4da19d04fa2217e2d5a1de /src/soc/intel/tigerlake | |
| parent | 11fae4ffe019ad648e517115aa1ec7bedbf4f648 (diff) | |
soc/intel/{icl,tgl,jsl,ehl}: add LPIT support
Add SLP_S0 residency register and enable LPIT support.
Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048
Reviewed-by: Lance Zhao
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pmc.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c7e10a9a69..9d073fa5f9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -43,6 +43,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index f926799c75..cd0299aa48 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -152,6 +152,8 @@ enum pch_pmc_xtal pmc_get_xtal_freq(void); #define HPR_CAUSE0_MI_HRPC (1 << 9) #define HPR_CAUSE0_MI_HR (1 << 8) +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) |