soc/intel/common: Adapt XHCI elog driver for reuse

Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS
or North XHCI block has a similar enough PCI MMIO structure to make this
code mostly reusable.

1) Rename everything to drop the `pch_` prefix
2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI
controller
3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI
controller

BUG=b:172279037
TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via
EC; type on keyboard, verify it wakes up, eventlog contains:
39 | 2020-12-10 09:40:21 | S0ix Enter
40 | 2020-12-10 09:40:42 | S0ix Exit
41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1
42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109
which verifies it still functions for the PCH XHCI controller

Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 30 insertions, 11 deletions

diff --git a/src/soc/intel/tigerlake/xhci.c b/src/soc/intel/tigerlake/xhci.c
index 18bb129983..6f095fa633 100644
--- a/src/soc/intel/tigerlake/xhci.c
+++ b/src/soc/intel/tigerlake/xhci.c
@@ -1,20 +1,39 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <device/pci_type.h>
 #include <intelblocks/xhci.h>
+#include <soc/pci_devs.h>
 
-#define XHCI_USB2_PORT_STATUS_REG	0x480
-#define XHCI_USB3_PORT_STATUS_REG	0x520
-#define XHCI_USB2_PORT_NUM		10
-#define XHCI_USB3_PORT_NUM		4
+#define PCH_XHCI_USB2_PORT_STATUS_REG	0x480
+#define PCH_XHCI_USB3_PORT_STATUS_REG	0x520
+#define PCH_XHCI_USB2_PORT_NUM		10
+#define PCH_XHCI_USB3_PORT_NUM		4
 
-static const struct xhci_usb_info usb_info = {
-	.usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG,
-	.num_usb2_ports = XHCI_USB2_PORT_NUM,
-	.usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
-	.num_usb3_ports = XHCI_USB3_PORT_NUM,
+#define TCSS_XHCI_USB2_PORT_STATUS_REG	0x480
+#define TCSS_XHCI_USB3_PORT_STATUS_REG	0x490
+#define TCSS_XHCI_USB2_PORT_NUM		1
+#define TCSS_XHCI_USB3_PORT_NUM		4
+
+static const struct xhci_usb_info pch_usb_info = {
+	.usb2_port_status_reg = PCH_XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = PCH_XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = PCH_XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = PCH_XHCI_USB3_PORT_NUM,
+};
+
+static const struct xhci_usb_info tcss_usb_info = {
+	.usb2_port_status_reg = TCSS_XHCI_USB2_PORT_STATUS_REG,
+	.num_usb2_ports = TCSS_XHCI_USB2_PORT_NUM,
+	.usb3_port_status_reg = TCSS_XHCI_USB3_PORT_STATUS_REG,
+	.num_usb3_ports = TCSS_XHCI_USB3_PORT_NUM,
 };
 
-const struct xhci_usb_info *soc_get_xhci_usb_info(void)
+const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
 {
-	return &usb_info;
+	if (xhci_dev == PCH_DEVFN_XHCI)
+		return &pch_usb_info;
+	else if (xhci_dev == SA_DEVFN_TCSS_XHCI)
+		return &tcss_usb_info;
+
+	return NULL;
 }