diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-09-08 20:15:36 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-16 13:59:58 +0000 |
| commit | 8407c3464c9f1cbe13288a5eda9fa4be7e70020c (patch) | |
| tree | f7d3db668eb162e7203e6ef2703fd95e3bd530c4 /src/soc/intel/tigerlake/uart.c | |
| parent | 06a892240d0ea0fa8e3c278bba429dea94fc84b5 (diff) | |
soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_TCSS at SoC level
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC
Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from
specific mainboard (brya) to ensure all Alder Lake mainboards can make
use of common TCSS block.
BUG=b:187385592
TEST=Type-C pendrive/Gen-2 SSD detected as Super speed.
Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/tigerlake/uart.c')
0 files changed, 0 insertions, 0 deletions