soc/intel/*: drop UART pad configuration from common code

UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.

Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.

Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao

1 files changed, 6 insertions, 34 deletions

diff --git a/src/soc/intel/tigerlake/uart.c b/src/soc/intel/tigerlake/uart.c
index da392f434b..fa4760c118 100644
--- a/src/soc/intel/tigerlake/uart.c
+++ b/src/soc/intel/tigerlake/uart.c
@@ -6,41 +6,13 @@
  * Chapter number: 9
  */
 
-#include <device/pci_def.h>
-#include <intelblocks/gpio.h>
-#include <intelblocks/lpss.h>
-#include <intelblocks/pcr.h>
-#include <intelblocks/uart.h>
-#include <soc/iomap.h>
-#include <soc/pch.h>
+#include <commonlib/helpers.h>
 #include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
 
-const struct uart_controller_config uart_ctrlr_config[] = {
-	{
-		.console_index = 0,
-		.devfn = PCH_DEVFN_UART0,
-		.gpios = {
-			PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
-			PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
-		},
-	},
-	{
-		.console_index = 1,
-		.devfn = PCH_DEVFN_UART1,
-		.gpios = {
-			PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
-			PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
-		},
-	},
-	{
-		.console_index = 2,
-		.devfn = PCH_DEVFN_UART2,
-		.gpios = {
-			PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
-			PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
-		},
-	}
+const unsigned int uart_devices[] = {
+	PCH_DEVFN_UART0,
+	PCH_DEVFN_UART1,
+	PCH_DEVFN_UART2,
 };
 
-const int uart_ctrlr_config_size = ARRAY_SIZE(uart_ctrlr_config);
+const int uart_devices_size = ARRAY_SIZE(uart_devices);