summaryrefslogtreecommitdiff
path: root/src/soc/intel/tigerlake/spi.c
diff options
context:
space:
mode:
authorWonkyu Kim <wonkyu.kim@intel.com>2020-01-22 23:48:52 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-01-25 10:44:03 +0000
commit06e067e4cf7a7b455a4574c3c62391de23973bb7 (patch)
tree0399f0c3722a5ffad0e1d86543941ebde2dfe257 /src/soc/intel/tigerlake/spi.c
parent591b0ff535d36f0f69e92c55fe465cbf70dcbfe4 (diff)
mb/intel/tglrvp: Enable rp11 for optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk pins. This is also dependent on pciecontroller3 config to be set as 2x2 instead of 1x4 in fit configuration in IFWI. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices from lspci Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/spi.c')
0 files changed, 0 insertions, 0 deletions