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| author | Duncan Laurie <dlaurie@google.com> | 2020-07-29 16:31:18 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-10-09 23:26:04 +0000 |
| commit | a5bb31f069d709f2ca9ddda4f623147df9653990 (patch) | |
| tree | 5efec6a8b9fad77214ac84d9b4c14d79f0fc3bb4 /src/soc/intel/tigerlake/spi.c | |
| parent | e335c2e02fcf7ee15dd5ae947a19d65390729263 (diff) | |
soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception
of some essential devices.
Set a default register value as an example.
Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44038
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/spi.c')
0 files changed, 0 insertions, 0 deletions