diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-23 00:06:07 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-28 18:36:52 +0000 |
| commit | 9f2e3ad6280000b818c71ebd250430509a819553 (patch) | |
| tree | 544a91b954b537f298eb0ebd0cb0cea4d86aef9c /src/soc/intel/tigerlake/romstage | |
| parent | 61657c2fae46e1ed8e2a4ddd42a2aa3caa8accfa (diff) | |
soc/intel/tigerlake: Enable DP ports according to board design
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux
from pinctl driver.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ia6e9271a11a1f9e6f98923772219ccc1e7daecda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38528
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index a4533c9e6c..6ed3dcd2de 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -84,6 +84,24 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, else m_cfg->InternalGfx = 0x1; + /* DP port config */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBConfig = config->DdiPortBConfig; + m_cfg->DdiPortAHpd = config->DdiPortAHpd; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPort1Hpd = config->DdiPort1Hpd; + m_cfg->DdiPort2Hpd = config->DdiPort2Hpd; + m_cfg->DdiPort3Hpd = config->DdiPort3Hpd; + m_cfg->DdiPort4Hpd = config->DdiPort4Hpd; + m_cfg->DdiPortADdc = config->DdiPortADdc; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + m_cfg->DdiPort1Ddc = config->DdiPort1Ddc; + m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; + m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; + m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ |