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| author | Angel Pons <th3fanbus@gmail.com> | 2020-01-15 00:49:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 12:54:00 +0000 |
| commit | 1db5bc7dac2bb592708f26dede339ffdf3246567 (patch) | |
| tree | d8636a114ebd6ef6830a016de15c92b21f0b740d /src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | |
| parent | 3663d55a23fb64ea88dd1fd18ae4b0ce29e71a61 (diff) | |
nb/intel/haswell: Tidy up code and comments
- Reformat some lines of code
- Put names to all used MCHBAR registers
- Move MCHBAR registers into a separate file, for future expansion
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
Tested, it does not change the binary of Asrock B85M Pro4.
Change-Id: I926289304acb834f9b13cd7902801798f8ee478a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38434
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage/fsp_params_tgl.c')
0 files changed, 0 insertions, 0 deletions