diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-01 18:23:33 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-11-09 03:26:23 +0000 |
| commit | baf6d6e203ed0fae762f40ba73c576034b6ffc40 (patch) | |
| tree | 2f62580b1b4653b0de41bcc3263feaededcca08f /src/soc/intel/tigerlake/romstage/Makefile.inc | |
| parent | 930c31c63ab2e2a2654090f4968217f2cd3125f3 (diff) | |
soc/intel/tigerlake/romstage: Do initial SoC commit till romstage
Clone entirely from Icelake
List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Remove and clean below files
5.a Clean up upd override in fsp_params.c,
will be added once FSP available.
5.b Remove __weak functions from fsp_params.c
6. Add CPU/PCH/SA EDS document number and chapter number
7. Add required headers into include/soc/ from ICL directory
Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36552
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage/Makefile.inc')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/Makefile.inc | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/Makefile.inc b/src/soc/intel/tigerlake/romstage/Makefile.inc new file mode 100644 index 0000000000..8d151e3871 --- /dev/null +++ b/src/soc/intel/tigerlake/romstage/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Intel Corporation +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += fsp_params.c +romstage-y += ../../../../cpu/intel/car/romstage.c +romstage-y += romstage.c +romstage-y += pch.c +romstage-y += systemagent.c |