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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-04-21 13:52:50 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-05-06 04:12:41 +0000
commita137201edd37feceb392085b30f82fce3497ff36 (patch)
treec9bc3a89521e0e7ece9d0e3cfece3cffcdf47acc /src/soc/intel/tigerlake/include
parent87b7ec2ebb94d3c3c14c2fd6ec34ad80af950767 (diff)
soc/intel/tigerlake: Add known CPU Port IDs for GPIO communities
Change-Id: I97c00e1985f319ff1db57314723d8405c2a6cbd2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include')
-rw-r--r--src/soc/intel/tigerlake/include/soc/pcr_ids.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pcr_ids.h b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
index 319558aeba..03d36bf4f0 100644
--- a/src/soc/intel/tigerlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/tigerlake/include/soc/pcr_ids.h
@@ -31,6 +31,12 @@
#define PID_ESPI 0xc7
#define PID_SERIALIO 0xcb
+/* CPU Port IDs */
+#define PID_CPU_GPIOCOM0 0xb7
+#define PID_CPU_GPIOCOM1 0xb8
+#define PID_CPU_GPIOCOM4 0xb9
+#define PID_CPU_GPIOCOM5 0xba
+
/*
* SPI - DMI Destination ID
*/