soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC

Below changes are implemented:
1. Move HFSTS1 register definition to SoC since HFSTS1 register definition
   is specific to a SoC. Moving structure back to SoC specific to avoid
   unnecessay SoC specific macros in the common code.

2. Define a set of APIs in common code since CSE operation modes and
   working states are same across SoCs.
	cse_is_hfs1_com_normal(void)
	cse_is_hfs1_com_secover_mei_msg(void)
	cse_is_hfs1_com_soft_temp_disable(void)
	cse_is_hfs1_cws_normal(void)

3. Modify existing code to use callbacks to get data of me_hfs1 structure.

TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards.

Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

1 files changed, 43 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h
new file mode 100644
index 0000000000..3baa0045bd
--- /dev/null
+++ b/src/soc/intel/tigerlake/include/soc/me.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _TIGERLAKE_ME_H_
+#define _TIGERLAKE_ME_H_
+
+/* ME Host Firmware Status register 1 */
+union me_hfsts1 {
+	u32 data;
+	struct {
+		u32 working_state: 4;
+		u32 spi_protection_mode: 1;
+		u32 fpt_bad: 1;
+		u32 operation_state: 3;
+		u32 fw_init_complete: 1;
+		u32 ft_bup_ld_flr: 1;
+		u32 update_in_progress: 1;
+		u32 error_code: 4;
+		u32 operation_mode: 4;
+		u32 reset_count: 4;
+		u32 boot_options_present: 1;
+		u32 invoke_enhance_dbg_mode: 1;
+		u32 bist_test_state: 1;
+		u32 bist_reset_request: 1;
+		u32 current_power_source: 2;
+		u32 reserved: 1;
+		u32 d0i3_support_valid: 1;
+	} __packed fields;
+};
+
+#endif /* _TIGERLAKE_ME_H_ */