diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-23 22:02:20 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-23 06:31:48 +0000 |
| commit | 85610d8d86de10cdb8c82b61290501ee0b3cf742 (patch) | |
| tree | 06e8e073dd06f153443a461d1dc5c61bc1d202bd /src/soc/intel/tigerlake/include | |
| parent | 74da5f1e7451c80b8a8420dc79d825074c6ca823 (diff) | |
soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers
Add NMI_EN and NMI_STS registers, so NMI interrupts can be used.
References:
- XEON-SP: Intel doc# 633935-005 and 547817 rev1.5
- ICL-LP: Intel doc# 341081-002
- TGL-LP: Intel doc# 631120-001
- TGL-H: Intel doc# 636174-002
- JSL: Intel doc# 634545-001
- EHL: Intel doc# 636722-002
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
Diffstat (limited to 'src/soc/intel/tigerlake/include')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/gpio_defs.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h index 7f0827d5f6..c90931d80c 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h @@ -292,6 +292,8 @@ #define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #define PAD_CFG_BASE 0x700 #endif diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h index e27415e4ac..1a9b2f3b0d 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h @@ -310,6 +310,8 @@ #define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1c0 +#define GPI_NMI_EN_0 0x1e0 #define PAD_CFG_BASE 0x600 #endif |