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authorArthur Heymans <arthur@aheymans.xyz>2023-08-31 18:19:09 +0200
committerLean Sheng Tan <sheng.tan@9elements.com>2024-01-22 13:52:48 +0000
commit470f1d38857bfa08aab2991fe5f0080aa7dc2526 (patch)
tree781c4b10fb59b0e469ca780ef03ec2ac1a76e202 /src/soc/intel/tigerlake/graphics.c
parentf40e59c83867b04599b6c4b6d07ad0c7d51eb293 (diff)
soc/intel/xeon_sp: Scan and allocate resources on all stacks
The code can now deal with stacks that have no resources so just hook them all up. Intel XEON-SP FSP reports all report the state of its stacks, which comprise of PCI root bridges and their respective resources, like PCI busses, IO and MEM resources, via HOB. Parsing all of those into native coreboot structures makes it possible to handle those in a more native fashion like use PCI drivers, native helper functions, ... As opposed parsing those structures again out of the HOB each time. This makes code reuse across the tree more feasible. An additional advantage is that Linux does not need to redo resource allocation since the one done by coreboot will be valid, which potentially decreases boot time. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu@intel.com> Change-Id: Id72c6e4499e99df3b7ca821ab2893cbcc869dbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/78332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/tigerlake/graphics.c')
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