diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-08 19:22:07 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-20 16:36:28 +0000 |
| commit | 7d6bc60db9427f029f990002870e40541601a209 (patch) | |
| tree | 40b34a1431710e1be32205c5a2711664ab628244 /src/soc/intel/tigerlake/fsp_params.c | |
| parent | 32585de39ea15b4192e213b7cfcf46485bfd0d2f (diff) | |
tigerlake: enable DPTF functionality for volteer
Enable DPTF functionality for volteer platform
BRANCH=None
BUG=b:149722146
TEST=Built and tested on volteer system
Change-Id: I385fb409ccd291d97369295ff99f21c9430880f9
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41427
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index cf106cbe16..0c67105300 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -193,6 +193,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + /* Enable TCPU for processor thermal control */ + params->Device4Enable = config->Device4Enable; + /* LAN */ dev = pcidev_path_on_root(PCH_DEVFN_GBE); if (!dev) |