diff options
| author | Jes Klinke <jbk@google.com> | 2020-08-10 13:30:40 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-17 07:11:19 +0000 |
| commit | 6fd87ffe2e44ea8782446e00ac06f66612e32bec (patch) | |
| tree | cea45aa9d80775241acd63c15bca51fc7bebb09f /src/soc/intel/tigerlake/fsp_params.c | |
| parent | 1df3b70c6a2eeb922bae96991f0a93e43e7e9721 (diff) | |
soc/intel/tigerlake: Allow fine grained control of S0iX states
Expose devicetree parameter to enable/disable each individual substate.
See https://review.coreboot.org/c/coreboot/+/43741 for context.
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137
Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index a61a0255bc..0a5fbe71e0 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -204,6 +204,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* S0iX: Selectively enable individual sub-states, + * by default all are enabled. + * + * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4 + */ + params->LpmStateEnableMask = LPM_S0iX_ALL & ~config->LpmStateDisableMask; + /* * Power Optimizer for DMI and SATA. * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. |