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authorDuncan Laurie <dlaurie@google.com>2020-10-27 17:57:13 -0700
committerDuncan Laurie <dlaurie@chromium.org>2020-11-20 00:25:29 +0000
commit17e905ac48dd30cd7edf3dbad57415f5523c9364 (patch)
tree0b6419892e87623ea6b14f901186cc289d24af68 /src/soc/intel/tigerlake/fsp_params.c
parent9d0fde3dc57bddf3a8e27bedcb35bbccfec1099a (diff)
soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement
Expose a config option that allows enabling the FSP UPD which controls Precision Time Measurement for a particular PCIe root port. This UPD is enabled by default in FSP but interferes with achieving deeper S0ix substates so in order to prevent it from needing to be explicitly disabled for every root port this change makes disabling it the default and allows it to be enabled if needed. BUG=b:160996445 TEST=boot on volteer with PTM disabled by default for all root ports and ensure S0i3.2 substate can be achieved. Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46856 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 6de098aa3e..ed34897274 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -187,6 +187,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpAdvancedErrorReporting[i] =
config->PcieRpAdvancedErrorReporting[i];
params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+ params->PciePtm[i] = config->PciePtm[i];
}
/* Enable ClkReqDetect for enabled port */