soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design

This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):

1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH

In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. Deepest state expected on tigerlake up3 based
platforms is S0i3.2.

BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest
S0ix substate that is enabled is S0i3.1

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 53 insertions, 1 deletions

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index c0d712ca35..90d6805a76 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -3,7 +3,10 @@
 #include <assert.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <arch/pci_io_cfg.h>
+#include <device/pci_ops.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <fsp/api.h>
 #include <fsp/ppi/mp_service_ppi.h>
 #include <fsp/util.h>
@@ -50,6 +53,55 @@ static int get_l1_substate_control(enum L1_substates_control ctl)
 	return ctl - 1;
 }
 
+/* Function returns true if the platform is TGL-UP3 */
+static bool platform_is_up3(void)
+{
+	const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+	u32 cpu_id = cpu_get_cpuid();
+	uint16_t mchid = pci_read_config16(dev, PCI_DEVICE_ID);
+
+	if ((cpu_id != CPUID_TIGERLAKE_A0) && (cpu_id != CPUID_TIGERLAKE_B0))
+		return false;
+
+	return ((mchid == PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2) ||
+		(mchid == PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2));
+}
+
+static int get_disable_mask(struct soc_intel_tigerlake_config *config)
+{
+	int disable_mask;
+
+	/* Disable any sub-states requested by mainboard */
+	disable_mask = config->LpmStateDisableMask;
+
+	/* UP3 does not support S0i2.2/S0i3.3/S0i3.4 */
+	if (platform_is_up3())
+		disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2;
+
+	/* If external bypass is not used, S0i3 isn't recommended. */
+	if (config->external_bypass == false)
+		disable_mask |= LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4;
+
+	/* If external clock gating is not implemented, S0i3.4 isn't recommended. */
+	if (config->external_clk_gated == false)
+		disable_mask |= LPM_S0i3_4;
+
+	/*
+	 * If external phy gating is not implemented,
+	 * S0i3.3/S0i3.4/S0i2.2 are not recommended.
+	 */
+	if (config->external_phy_gated == false)
+		disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2;
+
+	/* If CNVi or ISH is used, S0i3.2/S0i3.3/S0i3.4 cannot be achieved. */
+	if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_BT)) ||
+		is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) ||
+		is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_ISH)))
+		disable_mask |= LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4;
+
+	return disable_mask;
+}
+
 static void parse_devicetree(FSP_S_CONFIG *params)
 {
 	const struct soc_intel_tigerlake_config *config;
@@ -234,7 +286,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
 	 * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4
 	 */
-	params->LpmStateEnableMask = LPM_S0iX_ALL & ~config->LpmStateDisableMask;
+	params->LpmStateEnableMask = LPM_S0iX_ALL & ~get_disable_mask(config);
 
 	/*
 	 * Power Optimizer for DMI and SATA.