soc/intel/tigerlake: Merge the recent change from other platforms

Merge the recent change from other platform(ICL/JSL).
- Update SKpMpInit setting
- Update APIs for getting dev info
- Update IGD related setting
- Update debug interface setting

BRANCH=none
TEST=build and boot ripto/volteer

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40349
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 13 insertions, 5 deletions

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 78cfb9f004..5acad201c6 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
+#include <fsp/ppi/mp_service_ppi.h>
 #include <fsp/util.h>
 #include <intelblocks/lpss.h>
 #include <intelblocks/xdci.h>
@@ -86,14 +87,21 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Load VBT before devicetree-specific config. */
 	params->GraphicsConfigPtr = (uintptr_t)vbt_get();
 
-	params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
-
+	/* Check if IGD is present and fill Graphics init param accordingly */
 	dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
 		params->PeiGraphicsPeimInit = 1;
 	else
 		params->PeiGraphicsPeimInit = 0;
 
+	/* Use coreboot MP PPI services if Kconfig is enabled */
+	if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
+		params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+		params->SkipMpInit = 0;
+	} else {
+		params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+	}
+
 	params->TcssAuxOri = config->TcssAuxOri;
 	for (i = 0; i < 8; i++)
 		params->IomTypeCPortPadCfg[i] = 0x09000000;
@@ -144,7 +152,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 			config->PcieRpAdvancedErrorReporting[i];
 	}
 	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (dev) {
 		if (!xdci_can_enable())
 			dev->enabled = 0;
@@ -159,7 +167,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
 
 	/* SATA */
-	dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
+	dev = pcidev_path_on_root(PCH_DEVFN_SATA);
 	if (!dev)
 		params->SataEnable = 0;
 	else {
@@ -173,7 +181,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	}
 
 	/* LAN */
-	dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
+	dev = pcidev_path_on_root(PCH_DEVFN_GBE);
 	if (!dev)
 		params->PchLanEnable = 0;
 	else