soc/intel/tigerlake: Do initial SoC commit till ramstage

Clone entirely from Icelake

List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Remove and clean below files
   5.a Clean up upd override in fsp_params.c,
	will be added once FSP available.
   5.b Remove __weak functions from fsp_params.c
   5.c Remove dGPU over PCIE enable Kconfig option
6. Add CPU/PCH/SA EDS document number and chapter number
7. Remove unnecessary headers from .c files based on review

Tiger Lake specific changes will follow in subsequent patches.
1. Include GPIO controller delta over ICL
2. FSP-S related UPD overrides as applicable

Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 126 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c
new file mode 100644
index 0000000000..ac9dc24b50
--- /dev/null
+++ b/src/soc/intel/tigerlake/finalize.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 4, 29
+ */
+
+#include <arch/io.h>
+#include <device/mmio.h>
+#include <bootstate.h>
+#include <console/console.h>
+#include <console/post_codes.h>
+#include <cpu/x86/smm.h>
+#include <device/pci.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/tco.h>
+#include <intelblocks/thermal.h>
+#include <reg_script.h>
+#include <spi-generic.h>
+#include <soc/p2sb.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <soc/smbus.h>
+#include <soc/soc_chip.h>
+#include <soc/systemagent.h>
+#include <stdlib.h>
+
+#define CAMERA1_CLK		0x8000 /* Camera 1 Clock */
+#define CAMERA2_CLK		0x8080 /* Camera 2 Clock */
+#define CAM_CLK_EN		(1 << 1)
+#define MIPI_CLK		(1 << 0)
+#define HDPLL_CLK		(0 << 0)
+
+static void pch_enable_isclk(void)
+{
+	pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK);
+	pcr_or32(PID_ISCLK, CAMERA2_CLK, CAM_CLK_EN | MIPI_CLK);
+}
+
+static void pch_handle_sideband(config_t *config)
+{
+	if (config->pch_isclk)
+		pch_enable_isclk();
+}
+
+static void pch_finalize(void)
+{
+	uint32_t reg32;
+	uint8_t *pmcbase;
+	config_t *config;
+	uint8_t reg8;
+
+	/* TCO Lock down */
+	tco_lockdown();
+
+	/*
+	 * Set low maximum temp threshold value used for dynamic thermal sensor
+	 * shutdown consideration.
+	 *
+	 * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
+	 * thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
+	 */
+	pch_thermal_configuration();
+
+	/*
+	 * Disable ACPI PM timer based on dt policy
+	 *
+	 * Disabling ACPI PM timer is necessary for XTAL OSC shutdown.
+	 * Disabling ACPI PM timer also switches off TCO
+	 *
+	 * SA_DEV_ROOT device is used here instead of PCH_DEV_PMC since it is
+	 * just required to get to chip config. PCH_DEV_PMC is hidden by this
+	 * point and hence removed from the root bus. pcidev_path_on_root thus
+	 * returns NULL for PCH_DEV_PMC device.
+	 */
+	config = config_of_soc();
+	pmcbase = pmc_mmio_regs();
+	if (config->PmTimerDisabled) {
+		reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
+		reg8 |= (1 << 1);
+		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
+	}
+
+	/* Disable XTAL shutdown qualification for low power idle. */
+	if (config->s0ix_enable) {
+		reg32 = read32(pmcbase + CPPMVRIC);
+		reg32 |= XTALSDQDIS;
+		write32(pmcbase + CPPMVRIC, reg32);
+	}
+
+	pch_handle_sideband(config);
+
+	pmc_clear_pmcon_sts();
+}
+
+static void soc_finalize(void *unused)
+{
+	printk(BIOS_DEBUG, "Finalizing chipset.\n");
+
+	pch_finalize();
+
+	printk(BIOS_DEBUG, "Finalizing SMM.\n");
+	outb(APM_CNT_FINALIZE, APM_CNT);
+
+	/* Indicate finalize step with post code */
+	post_code(POST_OS_BOOT);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, soc_finalize, NULL);
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, soc_finalize, NULL);