diff options
| author | Jan Samek <jan.samek@siemens.com> | 2023-01-23 13:21:21 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-27 14:36:23 +0000 |
| commit | 567c6be77a5cb501d361c33e5b53329c76c058bf (patch) | |
| tree | ca22b608e9e352f0bdea7c4e60963390f1960a23 /src/soc/intel/tigerlake/espi.c | |
| parent | 36f8b03a925728b4a23d905fe7832ddef0048c33 (diff) | |
mb/siemens/mc_apl1/var/mc_apl5: Enable early POST
Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.
BUG=none
TEST=Boot on mc_apl5 and observe that POST codes are
displayed before DRAM training.
Change-Id: I390e0ab09ca830637e7a991db77e994d6c358e75
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72386
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/espi.c')
0 files changed, 0 insertions, 0 deletions