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| author | Shaunak Saha <shaunak.saha@intel.com> | 2020-06-18 23:09:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:45:30 +0000 |
| commit | 148f8397d2793a465623877d311733eb82e4fe69 (patch) | |
| tree | 56cd70634daaeeb64affd5931c19aab5adb8bd0c /src/soc/intel/tigerlake/espi.c | |
| parent | 4276050d13cb8c555f0375d4ec44d33ab5d58402 (diff) | |
soc/intel/tigerlake: Disable CPU PCIe in FSP
In TGL SoC we have PCH and CPU side PCIe support. This patch
skips CPU side PCIe enablement in FSP if device is disabled in
devicetree. Disabling the initialization of CPU PCIe saves ~30ms
in FspSiliconInit!
BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the
boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/espi.c')
0 files changed, 0 insertions, 0 deletions