diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-11-03 13:16:27 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-09 07:38:47 +0000 |
| commit | 8a78f5903952f1dee3ecbde8b8ea613c78639d48 (patch) | |
| tree | 4a1abec64f3be62c828d57b37642c25c0e97e2d7 /src/soc/intel/tigerlake/elog.c | |
| parent | 8a1ad138225e5a31d75cd77b9d7f183f3ab6d39c (diff) | |
soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log
All wakes by a PCH PCIe root port were lumped under one event source;
this commit splits them up so each root port gets its own ID in the
event log.
BUG=b:172279061
BRANCH=volteer
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/elog.c')
| -rw-r--r-- | src/soc/intel/tigerlake/elog.c | 39 |
1 files changed, 37 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 84f0a7ed4f..a46afbb24c 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -2,11 +2,13 @@ #include <bootstate.h> #include <console/console.h> -#include <stdint.h> +#include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <stdint.h> +#include <types.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -20,6 +22,39 @@ static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) } } +static void pch_log_rp_wake_source(void) +{ + size_t i; + struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; + }; + + const struct pme_map pme_map[] = { + { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { + const struct device *dev = pcidev_path_on_root(pme_map[i].devfn); + if (!dev) + continue; + + if (pci_dev_is_wake_source(dev)) + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -32,7 +67,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* PCI Express (TODO: determine wake device) */ if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + pch_log_rp_wake_source(); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) |