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| author | Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> | 2021-05-21 11:42:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-22 05:42:45 +0000 |
| commit | c8b22418aa9efe392267c979f000526e063676e6 (patch) | |
| tree | bcf20d2290be93ffbd45bf325cae67894de22e64 /src/soc/intel/tigerlake/cpu.c | |
| parent | 83faea00f5fc5fd518f83e1d7716de2f0f9aeef7 (diff) | |
util/spd_tools/lp4x: Add new memory part to to global memory definition
This new definition is for MT53E512M32D1NP-046 WT:B used on Cret.
BUG=b:183057749
TEST=Generate SPDs
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ica5df61d96d2c4cbe62a560a53bd3bd08eb121f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/cpu.c')
0 files changed, 0 insertions, 0 deletions