soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design

This change uses the following information to determine the
appropriate S0ix states to enable as per PDG document: 607872
for TGL UP3 UP Rev2p2 (section 10.13):

1. SoC - UP3 v/s UP4
2. H/W design - external phy gating, external clk gating, external bypass
3. Devices enabled at runtime - CNVi, ISH

In some cases, it is recommended to use a shallower state for
S0ix even if the higher state can be achieved (e.g. with external
gating not enabled). This recommendation is because the shallower
state is determined to provide better power savings as per the
above document. Deepest state expected on tigerlake up3 based
platforms is S0i3.2.

BUG=b:177821896
TEST=Build coreboot for volteer. Verify that deepest
S0ix substate that is enabled is S0i3.1

Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I5f2ac8b72d0c9b05bc02c092188d0c742cc83af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49766
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 24 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index edc716064f..cccf80476e 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -499,6 +499,30 @@ struct soc_intel_tigerlake_config {
 	 *  - PM_CFG.SLP_LAN_MIN_ASST_WDTH
 	 */
 	uint8_t PchPmPwrCycDur;
+
+	/*
+	 * External Clock Gate
+	 * true = Mainboard design uses external clock gating
+	 * false = Mainboard design does not use external clock gating
+	 *
+	 */
+	bool external_clk_gated;
+
+	/*
+	 * External PHY Gate
+	 * true = Mainboard design uses external phy gating
+	 * false = Mainboard design does not use external phy gating
+	 *
+	 */
+	bool external_phy_gated;
+
+	/*
+	 * External Bypass Enable
+	 * true = Mainboard design uses external bypass rail
+	 * false = Mainboard design does not use external bypass rail
+	 *
+	 */
+	bool external_bypass;
 };
 
 typedef struct soc_intel_tigerlake_config config_t;