soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg

In order for the SOC to be able to control the Aux line orientation for
Type-C ports that do not have a retimer, the IomTypeCPortPadCfg UPD needs
to be configurable through devicetree to correctly set the GPIO pins that
the SOC should use to flip orientation.

BUG=b:145220205
BRANCH=NONE
TEST=booted Volteer proto 2 and verified that the AUX channels flip
when the cable is flipped

Change-Id: I2e48adb624c7922170eafb8dfcaed680f008936e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40244
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 13 insertions, 0 deletions

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 3047037183..a32cebe594 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -222,6 +222,19 @@ struct soc_intel_tigerlake_config {
 	uint8_t TcssDma1En;
 
 	/*
+	 * IOM Port Config
+	 * If a port orientation needs to be controlled by the SOC this setting must be
+	 * updated to reflect the correct GPIOs being used for the SOC port flipping.
+	 * There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
+	 * 0,1 are pull up and pull down for port 0
+	 * 2,3 are pull up and pull down for port 1
+	 * 4,5 are pull up and pull down for port 2
+	 * 6,7 are pull up and pull down for port 3
+	 * values to be programmed correspond to the GPIO family and offsets
+	 */
+	uint32_t IomTypeCPortPadCfg[8];
+
+	/*
 	 * SOC Aux orientation override:
 	 * This is a bitfield that corresponds to up to 4 TCSS ports on TGL.
 	 * Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.