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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-03-13 00:54:30 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-03-15 12:54:40 +0000
commit4b9fa2d6ea6107cf0c94b116dfffa553075fcded (patch)
tree14a76e06dbd8d2871e500b88c92786969b915a3b /src/soc/intel/tigerlake/chip.h
parent1db5bc7dac2bb592708f26dede339ffdf3246567 (diff)
soc/intel/tigerlake: Update Cpu Ratio settings
Add config to override CpuRatio or setting CpuRatio to allowed maximum processor non-turbo ratio. BUG=151175469 BRANCH=none TEST=Build and boot tglrvp and observe there is no extra reset in meminit. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
-rw-r--r--src/soc/intel/tigerlake/chip.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 9fc70f8a46..5e010bda59 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -285,6 +285,18 @@ struct soc_intel_tigerlake_config {
* This mode makes FSP detect Optane and NVME and set PCIe lane mode
* accordingly */
uint8_t HybridStorageMode;
+
+ /*
+ * Override CPU flex ratio value:
+ * CPU ratio value controls the maximum processor non-turbo ratio.
+ * Valid Range 0 to 63.
+ * In general descriptor provides option to set default cpu flex ratio.
+ * Default cpu flex ratio 0 ensures booting with non-turbo max frequency.
+ * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
+ * Only override CPU flex ratio to not boot with non-turbo max.
+ */
+ uint8_t cpu_ratio_override;
+
};
typedef struct soc_intel_tigerlake_config config_t;