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| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-05-13 13:07:23 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:33:51 +0000 |
| commit | d7b9e363e3ec09eb5e2977d16085fdb3cd1334ce (patch) | |
| tree | 29f04cde2a74d7daff68c7d4bcfe8dfc46200f31 /src/soc/intel/tigerlake/chip.h | |
| parent | 7f5f9331d1c8bc6012b4179018079e1b6aedc665 (diff) | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163
Update FSP headers for Tiger Lake platform generated based FSP
version 3163, which includes below additional UPDs:
FSPM:
TcssDma0En
TcssDma1En
FSPS:
PchFivrExtV1p05RailEnabledStates
PchFivrExtV1p05RailSupportedVoltageStates
PchFivrExtVnnRailEnabledStates
PchFivrExtVnnRailSupportedVoltageStates
PchFivrExtVnnRailSxVoltage
PchFivrExtV1p05RailIccMaximum
CstateLatencyControl5TimeUnit
VmdEnable
BUG=none
BRANCH=none
TEST=build and boot ripto/volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Icc893073629df59aef60162bed126d1f4b936e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41377
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
0 files changed, 0 insertions, 0 deletions