diff options
| author | John Zhao <john.zhao@intel.com> | 2020-05-13 15:40:07 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:34:08 +0000 |
| commit | 7a05e6e2ad75dc1e28a50f3f309d8e7aecaf2526 (patch) | |
| tree | 419240764873aca2adff99689a764b1cec84c39c /src/soc/intel/tigerlake/chip.h | |
| parent | d7b9e363e3ec09eb5e2977d16085fdb3cd1334ce (diff) | |
soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En
This adds FSP UPD TcssDma0En and TcssDma1En for configuration.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I04af970f74ab9dfe84f9c0c09ec2098e0093fa57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index c98fb667cc..3047037183 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -213,10 +213,14 @@ struct soc_intel_tigerlake_config { FORCE_ENABLE, } CnviBtAudioOffload; - /* Tcss */ + /* Tcss USB */ uint8_t TcssXhciEn; uint8_t TcssXdciEn; + /* Tcss DMA */ + uint8_t TcssDma0En; + uint8_t TcssDma1En; + /* * SOC Aux orientation override: * This is a bitfield that corresponds to up to 4 TCSS ports on TGL. |