summaryrefslogtreecommitdiff
path: root/src/soc/intel/tigerlake/chip.c
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2020-05-26 18:33:22 +0530
committerFurquan Shaikh <furquan@google.com>2020-07-21 22:57:49 +0000
commitb622d4b27b0ebff33cab63ff1ea52c285d68e028 (patch)
treea3adeadccdb620e9d622d4a3373975bacbc2f9bb /src/soc/intel/tigerlake/chip.c
parentf6b2e6f836d74b2b3c024230834651ff237fd884 (diff)
soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2
This patch performs below operations 1. Add support for FSP 2.2 2. Set EnableMultiPhaseSiliconInit to ensure bootloader can call FspMultiPhaseSiInit() API. 3. Provide placeholder to perform require chipset programming (example TCSS) before calling FspMultiPhaseSiInit() API. Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.c')
0 files changed, 0 insertions, 0 deletions